The present invention relates to a method of manufacturing a semiconductor device having accurate and uniform field dielectric regions. The present invention is applicable to manufacturing high speed integrated circuits having submicron design features and high conductivity reliable interconnect structures.
Current demands for high density and performance associated with ultra large scale integration require design rules of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. As device scaling plunges into the deep sub-micron ranges, it becomes increasingly difficult to maintain performance and reliability.
Devices built on the semiconductor substrate of a wafer must be isolated. Isolation is important in the manufacture of integrated circuits which contain a plethora of devices in a single chip because improper isolation of transistors causes current leakage which, in turn, causes increased power consumption leading to increased noise between devices.
In the manufacture of conventional complementary metal oxide semiconductor (CMOS) devices, isolation regions, called field dielectric regions, e.g., field oxide regions, are formed in a semiconductor substrate of silicon dioxide by local oxidation of silicon (LOCOS) or by shallow trench isolation (STI).
In the LOCOS method, an inert layer, such as a nitride layer is typically formed on a pad oxide layer on a semiconductor substrate. Thereafter, a patterned photoresist mask is formed on the nitride layer and the nitride layer-pad oxide is etched to expose areas in the substrate selected for LOCOS formation. The pad is removed, and localized regions of silicon oxide are then grown in the exposed areas and the nitride layer is removed. In the STI method, a barrier layer, such as an oxide is typically formed on a semiconductor substrate and an inert layer, such as a nitride, is formed on the barrier layer. A photoresist mask is formed on the nitride layer and the nitride, barrier oxide and substrate are etched to form shallow trenches in the semiconductor substrate. Photoresist is then removed, and the resulting shallow trenches are filled with a dielectric material.
Photolithography is conventionally employed to transform complex circuit diagrams into patterns which are defined on the wafer in a succession of exposure and processing steps to form a number of superimposed layers of insulator, conductor and semiconductor materials. Scaling devices to smaller geometries increases the density of bits/chip and also increases circuit speed. The minimum feature size, i.e., the minimum line-width or line-to-line separation that can be printed on the surface, controls the number of circuits that can be placed on the chip and directly impacts circuit speed. Accordingly, the evolution of integrated circuits is closely related to and limited by photolithographic capabilities.
An optical photolithographic tool includes an ultraviolet (UV) light source, a photomask and an optical system. A wafer is covered with a photosensitive layer, called a resist, because of its ability to resist etchants. The mask is illuminated with UV light and the mask pattern is imaged onto the resist by the optical system. Photoresists are organic compounds whose solubility in a developer changes as a result of exposure to light or x-rays. The exposed regions become either more soluble or less soluble in a developer solvent.
There are, however, significant problems attendant upon the use of conventional LOCOS or STI methodology to form field dielectric regions in a semiconductor substrate. For example, when a photoresist is coated on a highly reflective surface, such as silicon nitride which has an index of refraction of about 2.00, and exposed to monochromatic radiation, undesirable xe2x80x9cswing effectsxe2x80x9d are produced as a result of interference between the reflected wave and the incoming radiation wave. In particular, swing effects are caused when the light waves propagate through a photoresist layer down to the silicon nitride layer, where they are reflected back up through the photoresist and through the silicon nitride to the sbstrate, when they are again reflected to the photoresist.
These swing effects cause the light intensity in the resist film to vary periodically as a function of resist thickness, thereby creating variations in the development rate along the edges of the resist and leading to uncontrolled line width variations. These reflections make it difficult to control critical dimensions (CDs) such as linewidth and spacing of the photoresist and have a corresponding negative impact on the CD control of the shallow isolation trenches.
There are further disadvantages attendant upon the use of conventional LOCOS and STI methodologies. For example, distortions in the photoresist are further created during passage of reflected light through the highly reflective silicon nitride layer which is typically used as a hardmask for STI etching. Specifically, normal fluctuations in the thickness of the silicon nitride layer cause a wide range of varying reflectivity characteristics across the silicon nitride layer, further adversely affecting the ability to maintain tight CD control of the photoresist pattern and the resulting shallow isolation trenches.
Highly reflective transparent substrates accentuate the swing effects, and thus one approach to addressing the problems associated with the high reflectivity of the silicon nitride layer has been to attempt to suppress such effects through the use of dyes and anti-reflective coatings below the photoresist layer. For example, an anti-reflective coating (ARC), such a s a polymer film, has been deposited directly on the silicon nitride layer. The ARC serves to eliminate reflection of most of the radiation that penetrates the photoresist thereby reducing the negative effects stemming from the underlying reflective materials during photoresist patterning. Unfortunately, use of an ARC adds significant drawbacks with respect to process complexity. To utilize an organic or inorganic ARC, the process of manufacturing the semiconductor chip must include a process step for depositing the ARC material, and also a step for prebaking the organic ARC or depositing a protective coating on the inorganic ARC before spinning the photoresist.
There exists a need for a cost effective, simplified processes enabling the formation of an ARC to prevent the negative effects stemming from the underlying reflective materials during photoresist patterning.
The present invention addresses and solves the problems attendant upon conventional multi-step, time-consuming and complicated processes for manufacturing semiconductor devices utilizing an ARC.
An advantage of the present invention is an efficient cost-effective method of manufacturing a semiconductor device with accurately formed field dielectric regions.
Additional advantages of the present invention will be set forth in the description which follows, and in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises:
forming an oxide layer on a semiconductor substrate;
forming a silicon nitride layer on the oxide layer in a chamber;
forming an amorphous (xcex1)-silicon anti-reflective coating on the silicon nitride layer in the chamber; and
Embodiments of the present invention include forming the xcex1-silicon layer and the silicon nitride layer in the sane deposition chamber.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.